1. Field of the Invention
The present invention relates to an input signal variation detection circuit, and in particular, to an improved input signal variation detection circuit for detecting transitions of input signals from a memory apparatus.
2. Background of the Related Art
FIG. 1A is a block diagram illustrating an input signal variation detection circuit of a related art, which includes a plurality of unit blocks UB1 through UBn, and a summation block SB. The corresponding unit blocks UB1-UBn detect transitions of signals AN1 through ANn and output transition detection signals ATD1 through ATDn. The summation block SB outputs a summation signal ATDSUM in accordance with the transition detection signals ATD1 through ATDn from the unit blocks UB1 through UBn.
Each unit block UBx (1.ltoreq..times..ltoreq.n) of the unit blocks UB1 through UBn, is shown in Figure 1B. An inverter 10 inverts an input signal ANx, and an inverter 12 inverts the output signal from the inverter 10 and outputs the signal to a node a1. An inverter 14 inverts the output signal from the inverter 12 and outputs the signal to a node a2. A transmission gate 16 receives the signal from the node a2 through an NMOS transistor 20, and the signal from the node a1 through a PMOS transistor 18 to control the transmission of the input signal ANx. A PMOS transistor 18 has the gate coupled for receiving the input signal ANx, the source coupled for receiving the signal from the node a1, and the drain coupled to the output terminal of the transmission gate 16 for outputting the transition detection signal ATDx. An NMOS transistor 20 has the drain connected to the drain of the PMOS transistor 18, the gate coupled for receiving the input signal ANx, and the source commonly connected with the output terminal of the inverter 14 through the node a2 and the NMOS transistor of the transmission gate 16.
The summation block SB is shown in FIG. 1C. NMOS transistors NM1 through NMn have the gates coupled for receiving transition detection signals ATD1 through ATDn from the unit blocks UB1 through UBn, respectively. Each of the sources is coupled for receiving a ground voltage Vss, and each of the drains is connected to a common node b1. An inverter 22 inverts the signal from the common node b1, and an inverter 24 inverts the output signal from the inverter 22. A NOR-gate 26 logically NORs the output signal from the inverter 24 and the signal from the common node b1, and an inverter 28 inverts the output signal from the NOR-gate 26. A PMOS transistor 30 has the gate coupled for receiving the output signal from the inverter 28, the source coupled for receiving the voltage VCC, and the drain connected to the common node b1. An inverter 32 inverts the signal from the common node b1 and outputs a summation signal ATDSUM.
The operation of the input signal variation detection circuit is as follows. First, if the input signal ANx is a low level or a high level, the unit block UBx always outputs a low level transition detection signal ATDx.
When the input signal ANx transits from a high level to a low level, the PMOS transistor 18 is turned on, and the NMOS transistor 20 is turned off. Hence, the high level signal from the source of the PMOS transistor 18 is outputted as a transition detection signal ATDx. The inverter 10 outputs a high level signal to the inverter 12, and the inverter 12 outputs a low level signal. Therefore, the output signal from the inverter 12 is delayed for a predetermined time after the transit of the input signal ANx from a high level to a low level. If the inverter 12 outputs a low level signal, and the inverter 14 outputs a high level signal, the transmission gate 16 is turned on, and the low level input signal ANx passed through the transmission gate 16, and the low level signal from the source of the PMOS transistor 18 is outputted as a transition detection signal ATDx.
As a result, if the input signal ANx transits from a high level to a low level, the inverters 10 and 12 maintain a turned-off state for a predetermined time. The transition detection signal ATDx from the unit block UBx becomes a high level pulse signal for a predetermined time.
In addition, if the input signal ANx transits from a low level to a high level, the PMOS transistor 18 is turned off, and the NMOS transistor 20 is turned on. The transition gate 16 maintains a turned-on state for a predetermined delay time due to the inverters 10 and 12, and the high level signal passing through the transmission gate 16 is outputted as the transition detection signal ATDx.
After a lapse of the predetermined delay time by the inverters 10 and 12, the output signal from the inverter 12 transits from a low level to a high level, and the output signal from the inverter 14 transits from a high level to a low level, and the transmission gate 16 is turned off. Therefore, the low level signal from the inverter 14 is outputted through the NMOS transistor 20 as a transition detection signal ATDx.
As a result, if the input signal ANx transits from a low level to a high level, the unit block UBx outputs the transition detection signal ATD1, which is high level pulse signal, which is delayed by the inverters 10 and 12, for a predetermined time.
As shown in FIG. 1C, the summation block SB sums the transition detection signals ATD1 through ATDn from the unit blocks UB1 through UBn to output a summation signal ATDSUM. Namely, since the NMOS transistors (NM1 through NMn) are turned on while the transition detection signals ATD1 through ATDn are at a high level, the electric potential of the common node b1 is low level.
The signal from the common node b1 is sequentially inverted by the inverters 22 and 24 and is supplied to the NOR-gate 26. The NOR-gate 26 NORs the low level signal from the inverter 24 and the low level signal from the common node b1 to output a high level signal to the inverter 28. The inverter 28 inverts the inputted high level signal and outputs a low level signal to the gate of the PMOS transistor 30, which turns on the PMOS transistor 30. Therefore, the voltage VCC is supplied to the common node b1 through the PMOS transistor 30. As a result, the inverter 32 inverts the low level signal from the common node b1 and outputs a summation signal ATDSUM which is a pulse signal having the level of the voltage VCC.
However, in the input signal variation detection circuit of the background art, the speed for detecting the transition of the input signal is determined by the capacity, e.g., the number, of inverters within the unit blocks. Therefore, it is not possible to obtain high speed operation, and low electrical power consumption.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.